1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit including a circuit which performs high-speed and/or large-current switching, such as a driver circuit or the like.
2. Description of the Related Art
FIG. 1 illustrates a driving circuit which uses a CMOS (complementary metal oxide semiconductor) inverter. In FIG. 1, a control circuit 101 outputs a control signal 104 to a predriver 107 based on a signal from the outside or a signal within an IC (integrated circuit) including the driving circuit. The predriver 107 is an inverter comprising a pMOS transistor M101 and an nMOS transistor M102. The predriver 107 inverts the output 104 of the control circuit 101, and drives gates of a driver 108 at the final stage comprising a pMOS transistor M103 and an nMOS transistor M104. The pMOS transistor M103 and the nMOS transistor M104 constituting the driver 108 are large enough to charge/discharge a load capacitance C101 at a desired speed. There are also shown a positive power-supply line 102, a GND (ground) line 103, and an output 106. An output 105 of the predriver 107 is inverted by the driver 108 to provide the output 106. The load capacitance C101 may be the capacitance of a gate within the IC, or a load at the outside of the IC.
In Japanese Patent Laid-Open Application (Kokai) No. 5-235275 (1993), a method is proposed in which, in order to suppress noise from a power supply, a bypass capacitance is provided between power supply lines, and a thin-film resistor is connected in series in order to prevent destruction of the capacitance. This method will be described with reference to FIGS. 2(A) and 2(B). FIG. 2(A) is a schematic plan view, and FIG. 2(B) is a schematic cross-sectional view taken along line 2Bxe2x80x942B shown in FIG. 2(A).
In FIGS. 2(A) and 2(B), reference numeral 11 represents a silicon substrate as the one used in an ordinary silicon integrated circuit. A first field insulating layer 12 (about 500 nm thick) is formed using silicon oxide. A first conductive layer 13 (about 500 nm thick) is formed using aluminum. However, any other appropriate metal, polysilicon or the like may also be used for forming the first conductive layer 13. The first conductive layer 13 serves as a lower electrode of a capacitor, and an extended portion of the first conductive layer 13 operates as one of a set of power-supply lines (for example, a ground line). A dielectric layer. 14 (about 50 nm thick) is formed using silicon nitride. A second field insulating layer 15 (about 500 nm thick) is formed using silicon oxide. A thin-film resistive layer 16 (about 10 nm thick) is formed using a thin-film SiCr-type or NiCr-type resistive material. The resistance value of this thin-film resistive layer 16 is about 1-2 kxcexa9. A third field insulating layer 17 (about 150 nm thick) is formed using silicon oxide. There are also shown openings for contact 18a and 18b. A second conductive layer 19a and a third conductive layer 19b (both about 1,000 nm thick) are formed using aluminum. However, any other appropriate metal, polysilicon or the like may also be used for forming these conductive layers. The second conductive layer 19a serves as an upper electrode of the capacitor, and an extended portion of the second conductive layer 19a is connected to one end of the thin-film resistive layer 16. The third conductive layer 19b is connected to the other end of the thin-film resistive layer 16, and an extended portion of the third conductive layer 19b operates as the other line of the power-supply lines (for example, a plus power-supply line).
As is apparent from the foregoing description, the first conductive layer 13, the dielectric layer 14 and the second conductive layer 19a at the opening 18a constitute a capacitor, which operates as a bypass capacitor. The capacitor and the thin-film resistive layer 16 constitute a series circuit, which is provided between the two power-supply lines (for example, between the ground line and the plus power-supply line) of the integrated circuit.
As described above, in the case shown in FIGS. 2(A) and 2(B), by providing the series circuit of the capacitance and the thin-film resistor between the power-supply lines of the integrated circuit, destruction of the coupling capacitance is prevented.
When using the driving circuit shown in FIG. 1 by forming it on a semiconductor substrate and encapsulating the IC in a package, a finite parasitic inductance is present in the package and bonding wires. Hence, when intending to perform high-speed and/or large-current switching, voltages in the power-supply line and the ground line within the IC change to apply a voltage exceeding the power-supply voltage to the transistor at the output stage, thereby, in some cases, degrading the reliability of the IC. In general, as the degree of integration of a device increases, the breakdown voltage decreases. Accordingly, when using a driving circuit as shown in FIG. 1, it is necessary to use a device of a lower degree of integration having an allowance in the breakdown voltage, thereby providing, in some cases, a disadvantage from the viewpoint of improvement in the performance and in the degree of integration.
Such a problem will now be described with reference to FIG. 3. The configuration shown in FIG. 3 is obtained by adding parasitic inductances L101 and L102 and parasitic resistances R101 and R102 caused by the package and bonding wires to the configuration shown in FIG. 1. In FIG. 3, the same components or signals as those shown in FIG. 1 are indicated by the same reference numerals, and further description thereof will be omitted.
In FIG. 3, a power-supply input terminal 114 provides the integrated circuit with a positive power supply. A power-supply input terminal 115 is connected to the ground. A positive power-supply interconnection 116 is formed on the semiconductor substrate. A ground interconnection 117 is also formed on the semiconductor substrate. A package (PKG) 118 encapsulates the integrated circuit. Changes in the power-supply lines 116 and 117 when the output 105 of the predriver changes will now be described. In a usually used package, such as a QFP (quad flat package) or the like, a parasitic inductance of about 10 nH, and a parasitic resistance of the order of 0.1 xcexa9 are present. Accordingly, when switching a current of 500 mA in 2 nsec, the electromotive force generated in the parasitic inductance is estimated to be:
V=L(di/dt)=10 nHxc3x97500 mA/2 nsec=2.5 V.
This variation is not neglible when a power-supply voltage of about 5-10 V is used. Actually, since a greater change occurs in current at the moment of switching, a larger variation occurs in the power-supply lines. Furthermore, since variations occur in both of the positive power-supply line and the ground line, a larger voltage is applied to the device at the output stage.
FIGS. 4(A) through 4(D) illustrate variations in time in the input voltage of the driver, the power-supply voltages, and the source-drain voltages of the MOS transistors at the output stage.
FIG. 4(A) is a diagram illustrating the waveform of the input voltage of the driver 108. FIG. 4(B) is a diagram illustrating the waveforms of voltages in the power-supply line and the ground line. FIGS. 4(C) and 4(D) illustrate the source-drain voltages of the pMOS transistor M103 and the nMOS transistor M104, respectively. When the input voltage rises at a time T1 shown in FIG. 4(A), the nMOS transistor M104 is gradually turned on, so that a current flows through the driver 108 and a current as a result of discharging electric charges stored in the load C101 flows through the nMOS transistor M104. At that time, voltage drops occur in the parasitic elements L101, R101, L102 and R102 shown in FIG. 3, so that, as shown in FIG. 4(B), the voltage in the positive power-supply line decreases and the voltage in the ground line increases (at a time T2 shown in FIG. 4(B)).
This change in current generates an inverse electromotive force in the parasitic inductances L101 and L102, to increase the voltage of the positive power-supply line and to decrease the voltage of the ground line (at a time T3 shown in FIG. 4(B)).
At the rise of the input voltage, a larger change occurs in the ground line where the amount of change in current is large. On the other hand, at the fall of the input voltage, a larger change occurs in the positive power-supply line because the pMOS transistor M103 charges the load C101.
After the time T3, the change becomes oscillatory or non-oscillatory depending on the vaules of L, R and C.
When the above-described changes occur in the power-supply lines, as shown in FIGS. 4(C) and 4(D), a voltage exceeding the power-supply voltage is applied between the source and the drain of each of the MOS transistors M103 and M104 at the output stage. When this voltage exceeds the on-breakdown voltage of each of the MOS transistors M103 and M104, the drain voltage increases as indicated by static characteristics shown in FIG. 5, resulting in, in some cases, a decrease in the reliability of the device, for example, because hot carriers are injected into the gate oxide film.
In the configuration shown in FIGS. 2(A) and 2(B), variations in the power-supply lines are mitigated to some extent, to prevent destruction of the capacitance. However, in the above-described driving circuit performing high-speed and/or large-current switching and other circuits, the device is not always protected only by providing a series circuit of a coupling capacitance and a protective resistance between power-supply lines. This fact will now be explained with reference to a schematic diagram of arrangement of circuits shown in FIG. 6. In FIG. 6, there are shown a series circuit 30 of a capacitance and a thin-film resistor, other integrated circuits 31 and 32 which do not perform high-speed and/or large-current switching, a driving circuit 33 which performs high-speed and large-current switching, interconnections of a power-supply voltage 34 and 35, parasitic resistances R36-R41 caused by the power-supply interconnections, and parasitic capacitances C42-C53 caused by the power-supply interconnections. L101 and L102, and R101 and R102 are parasitic inductances and parasitic resistances, respectively, caused by the package and bonding wires. Actually, parasitic elements are distributed in the form of distributed constants. In FIG. 6, however, parasitic elements are represented by xcfx80 circuits. The values of parasitic resistances and parasitic capacitances change depending on the lengths and the widths of wirings, the structure of interlayer films, and the like. In the case shown in FIG. 6, noise in the power-supply lines is mainly generated from the driving circuit 33 which performs high-speed and large-current switching. In the power supply interconnections near the circuit 31 arranged in the vicinity of the series circuit 30 of the capacitance and the thin-film resistor, variations in the power-supply lines caused by switching by the circuit 33 are small because the effect of the coupling capacitance is relatively great. However, the effect of the coupling capacitance of the series circuit 30 decreases as a device is separated from the series circuit 30, due to the influence of the parasitic elements of the power-supply lines. Accordingly, large voltages due to variations in the power-supply voltage are applied to devices constituting the driving circuit 33, and devices constituting the circuit 32 which is close to the driving circuit 33 and is separated from the series circuit 30, so that the above-described problems of destruction of the device and a decrease in the reliability of the device are, in some cases, not improved.
When using the thin-film resistor, it is necessary to add a surplus process for forming the thin-film resistor to ordinary processes for forming a C (complementary) MOS structure or bipolar transistors, resulting in an increase in the number of processes, and, in some cases, an increase in the wafer cost.
If it is intended to use a device having a sufficient margin in the breakdown voltage with respect to the power-supply voltage in order to solve the above-described problems, an advanced device of a high degree of integration cannot be used. Instead, it is necessary to use a device having inferior characteristics compared with such an advanced device because of having a long gate length, thereby causing problems such that, for example, a larger chip area is required for obtaining the same degree of driving capability, to increase the production cost, and the parasitic capacitance of the driver increases, thereby increasing power consumption.
Furthermore, variations in the power-supply lines on the semiconductor substrate may cause a misoperation in the control circuit or other circuits integrated on the same substrate. In order to solve such a problem, it is necessary to use a more complicated circuit having a better PSRR (power supply rejection ratio), resulting in an increase in the production cost.
For example, if the power-supply voltage is stable, a comparative potential of a comparator can be provided by resistive division using two resistors. However, when the power-supply voltage fluctuates, it is necessary to provide a band-gap voltage source.
Although, in the foregoing description, a driver circuit using CMOS transistors has been illustrated, the same problems also arise when bipolar transistors or Bi(bipoler)CMOS devices are used.
In the case of using bipolar transistors, the influence on the reliability when breakdown between the collector and the emitter occurs is smaller than when using CMOS devices. However, since the driving capability of bipolar transistors is larger, the influence on other circuits at switching is larger.
It is an object of the present invention to provide an integrated circuit including a circuit requiring high-speed and/or large-current driving, in which a decrease in the reliability due to a parasitic inductance caused by the package of the integrated circuit, bonding wires and the like is prevented so as to be able to utilize a power-supply voltage to a value closer to a breakdown voltage of devices.
It is another object of the present invention to provide an integrated circuit which can prevent a misoperation in circuits caused by variations in a power-supply voltage due to the influence of the above-described parasitic inductance.
According to one aspect, the present invention which achieves these objectives relates to a semiconductor integrated circuit including a circuit for performing switching, and a series circuit, including at least one resistance and at least one capacitance, disposed so as to be adjacent to the circuit and provided between a high-voltage-sided interconnection and a low-voltage-side interconnection of a power-supply voltage for the circuit.
The capacitance in the series circuit (RC series circuit) including the resistance and the capacitance within the above-described integrated circuit operates so as to supply the high-voltage power-supply line and the lowvoltage power-supply line (for example, a ground line) connected to the circuit performing switching (particularly, a circuit performing high-speed and/or large-current switching) with electric charges, to reduce the amount of change of current in the parasitic inductance, and to reduce an inverse electromotive force generated in the parasitic inductance. The resistance in the RC series circuit operates so as to prevent resonance by the parasitic inductances and the capacitance.
The semiconductor integrated circuit of the present invention includes another circuit which does not perform switching, and a high-voltage-side interconnection and a low-voltage-side interconnection of the power-supply voltage for the other circuit are electrically separated from the high-voltage-side interconnection and the low-voltage-side interconnection of the power-supply voltage for the switching circuit. The circuit which does not perform switching indicates a circuit which does not perform switching at all, or a circuit which performs switching but in which influence by voltage variations due to the parasitic inductance are negligible even if switching is performed. That is, by electrically""separating the high-voltage-side interconnection and the low-voltage-side interconnection of the powersupply voltage for the other circuit which does not perform switching from the high-voltage-side interconnection and the low-voltage-side interconnection of the power-supply voltage for the switching circuit, the switching circuit does not influence other circuits.
Furthermore, in the semiconductor integrated circuit of the present invention, by disposing the series circuit including at least one resistance and at least one capacitance at a position closest to a high-voltage-side bonding pad and a low-voltage-side bonding pad for supplying the integrated circuit with the power-supply voltage, between the high-voltage-side interconnection and the low-voltage-side interconnection for supplying respective circuits constituting the integrated circuit with the power-supply voltage. That is, by providing the RC series circuit at a position closest to the bonding pads for supplying the power-supply voltage than the circuit performing high-speed and/or large-current switching and other circuits, a current which is not absorbed by the RC series circuit in the current caused by switching by the switching circuit (particularly, the circuit performing high-speed and/or large-current switching) and voltage variations due to a parasitic resistance caused by the interconnections within the integrated circuit are minimized.
In the semiconductor integrated circuit of the present invention, by setting the values of the resistance and the capacitance constituting the RC series circuit to values so that the LCR series circuit comprising the parasitic inductance and the parasitic resistance does not oscillate, it is possible to prevent the possibility that the power-supply voltage oscillates due to introduction of the RC series circuit.